1. Field of the Invention
This invention relates to lead frames used to construct semiconductor devices. The invention is also directed to a method of forming a semiconductor device incorporating a lead frame.
2. Background Art
Recent demand for miniaturized, dense, resin-sealed semiconductor devices has lead to the development of semiconductor devices as shown at 10 in FIGS. 8 and 9. With this type of device, leads 12 are exposed at transverse back and side surfaces 14, 16, but do not project from either surface 14, 16. Such semiconductor devices 10 are commonly referred to in the industry as SON (Small Outline Non-leaded Packages) and QFN (Quad Flat Non-leaded Packages).
The semiconductor device 10 consists of a unit lead frame 17 with a rectangular support 18 having a surface 20 to which a semiconductor chip 22 is bonded. Four leads 12, which are part of the unit lead frame 17, are spaced around, and project from, each of four sides on a peripheral edge 24 on the support 18, and are electrically connected to the semiconductor chip 22 through conductive wires 26. The support 18, semiconductor chip 22, and wires 26 are sealed by a solidified resin material 28 to form an overall squared configuration for the semiconductor device 10.
The unit lead frame 17 is formed as part of a lead frame 30 (FIG. 10), which is in the form of a layer, which may be a belt, a strip, or a sheet of material. The lead frame 30 can be made from conductive material, such as copper or iron alloy, and may be processed, as by etching or the like, to produce the configuration shown in FIG. 10. The unit frame 17, shown in FIGS. 8 and 9, is shown in the hatched region in FIG. 10.
The lead frame 30 consists of several, and in this case nine, unit frames 17, 17a, 17b, 17c, 17d, 17e, 17f, 17g, 17h, having the same configuration as the unit lead frame 17, arranged in a matrix form and interconnected to each other and a guide rail 32 through a tie bar network 34.
Once the lead frame 30 is formed, the semiconductor chips 22 are secured on the support surfaces 20, as by using a binder or binding tape. An electrode 36 on each semiconductor chip 22 is electrically connected through a wire 26 to one of the leads 12. This subassembly is then resin sealed within the area bounded by the square border, as indicated by the line 38, which area encompasses a portion of the guide rail 32.
Once the resin is cured, a saw is used to cut lengthwise, in the direction of the arrow 40, along and through tie bars 42,44 between the unit frames 17, 17a, 17b and 17c, 17d, 17e and 17c, 17d, 17e and 17f, 17g, 17h. Two additional lengthwise cuts of width W are made as indicated at the lines 46, 48 where unit frames 17, 17a, 17b and unit frames 17f, 17g, 17h, respectively, are joined to the guide rail 32. Orthogonal cuts are made through tie bars 50, 52 and at lines 54, 56 to separate the individual semiconductor devices 10.
The process described above is desirable in that it permits simultaneous resin sealing of a plurality of semiconductor devices 10. With a common shape, a wide variety of products can be made.
However, there are a number of problems that result from the manufacturing process for the semiconductor device 10 described above with respect to FIGS. 8-10. One problem is a result of resin leakage which occurs at the guide rail 32. This problem can be explained with respect to exemplary unit frame 17, as shown also in FIG. 11. The resin 28 tends to migrate past the edges 58, 60 of the guide rail 32. By reason of the width of the guide rail 32, resin tends to accumulate on the back surface 14 over the leads 12, so as to form xe2x80x9cresin flashesxe2x80x9d 62, which are contiguous with the guide rail 32. If these resin flashes are not removed, they potentially prevent establishment of a proper electrical connection with a product to which the semiconductor device 10 is connected. As a result, the manufacturing process may require at last one additional step to remove the resin flashes 62.
Another problem relates to the resistance that is encountered as certain cuts, using a separating saw, or the like, are made. The tie bars 42, 44, 50, 52 can be cut with little resistance by the saw. The tie bars 42, 44, 50, 52 may have a width W1 (shown for exemplary tie bar 42 in FIG. 10) that is less than the width W of a cutting blade on the saw. However, the cuts at 46, 48, 54, 56 must be made through the solid guide rail 32 so that a cut equal to the width W of the saw blade is made in the guide rail 32. With the width W of the saw greater than the width W1 of the tie bars 42, 44, 50, 52, relatively little cutting resistance may be encountered, whereas in cutting the full width of the guide rail 32, there may potentially be a significantly higher resistance to cutting. This condition may lead to a peeling off of the leads 12 and/or the resin material 28 from the guide rail 32 and/or deformation of the guide rail 32 during the cutting process.
In one form, the invention is directed to a lead frame for a semiconductor device. The lead frame has a layer defining a first unit lead frame including a first support for a semiconductor chip and a plurality of leads spaced around the first support. The first support has a peripheral edge. The layer further defines a guide rail extending along at least a portion of the peripheral edge and connected to at least one of the leads. At least one notch is formed in the layer between the at least one lead and a part of the guide rail so as to define a first tie bar.
The lead frame may further include a second unit lead frame defined by the layer and connected to the first unit lead frame by at least a second tie bar. The second unit lead frame has a second support for a semiconductor chip and a plurality of leads spaced around the second support. The second support has a peripheral edge.
The second tie bar may connect between leads on the first and second unit lead frames.
In one form, this first support has a polygonal shape with a peripheral edge. The peripheral edge of the first support has first and second transverse, substantially straight edge portions. A guide rail extends along the first and second edge portions. At least one notch is located between the first edge portion and a part of the guide rail. There is a second notch in the layer between the second edge portion and another part of the guide rail.
The first and second notches may extend fully through the layer.
In one form, the first unit lead frame consists of a plurality of leads extending along the first edge portion a first distance. In one form, the at least one notch extends along the first edge a distance equal to at least the first distance.
The first unit lead frame may include a plurality of leads extending along the first edge portion, with the first tie bar connected between the plurality of leads.
In one form, there is a third tie bar that connects between the first tie bar and the part of the guide rail.
The invention is also directed to a lead frame for a plurality of semiconductor devices, which lead frame has a layer defining a plurality of unit lead frames each consisting of a support for a semiconductor chip and a plurality of leads spaced around the support. The support has a peripheral edge. The layer defines a guide rail. The layer further defines a first tie bar connecting to a lead on a first unit lead frame in the plurality of unit lead frames and a second tie bar connecting between the first tie bar and a part of the guide rail.
The peripheral edge of the support on the first unit lead frame may be polygonal with first and second transverse, substantially straight, edge portions. The first tie bar may extend substantially parallel to the first edge portion, with the second tie bar extending transversely to the first edge portion.
The first tie bar may connect to a lead connected to the first edge portion.
In one form, there is a third tie bar that extends substantially parallel to the second edge portion. There is a fourth tie bar that connects between the third tie bar and another part of the guide rail. The third tie bar is connected to a lead connected to the second edge portion.
The part and the another part of the guide rail may each be elongate and extend substantially orthogonally to each other.
In one form, there are interconnected tie bars that extend substantially continuously fully around the support on the first unit lead frame.
In one form, a plurality of the interconnected tie bars define a shape around the peripheral edge of the first unit lead frame corresponding to a shape of the peripheral edge of the first unit lead frame.
The shape of the peripheral edge of the first unit lead frame may be substantially square.
In one form, the layer is a conductive sheet.
A plurality of the interconnected tie bars may have a substantially uniform width substantially fully around the peripheral edge of the first unit lead frame.
The invention is also directed to a lead frame for a plurality of semiconductor devices. The lead frame has a layer defining first and second unit lead frames each including a support for a semiconductor chip and a plurality of leads spaced around each support. The first and second unit lead frames are connected to each other through a tie bar network. The lead frame further includes a guide rail. The first unit lead frame is connected to the guide rail by at least a first tie bar and to the second unit lead frame by at least a second tie bar. The at least first and second tie bars have a width that is substantially the same.
In one form, a plurality of the tie bars have substantially the same width and extend substantially fully around the support on the first unit lead frame.
In one form, the support of the first unit lead frame has a peripheral edge with a polygonal shape and a plurality of tie bars that extend around the support on the first unit lead frame have a shape substantially corresponding to the shape of the peripheral edge on the first unit lead frame.
The invention is also directed to a method of manufacturing semiconductor devices. The method includes the steps of: forming a conductive layer consisting of a first plurality of unit lead frames each having a support for a semiconductor chip, a plurality of leads spaced around the support, and a tie bar network which interconnects the support to the leads on each of the unit lead frame and the plurality of unit lead frames to each other, the step of forming a conductive layer further including connecting the plurality of unit lead frames to a guide rail so that a second plurality of unit lead frames within the first plurality of unit lead frames are connected to the guide rail through the tie bar network and so that there are a plurality of tie bars which extend substantially fully around the support on each of the unit lead frames in the second plurality of unit lead frames; placing a semiconductor chip on each support on each of the first plurality of unit lead frames; electrically connecting the semiconductor chip on each unit lead frame to the respective leads on each unit lead frame; resin sealing at least a part of the conductive layer and a plurality of the semiconductor chips; and separating individual semiconductor devices by cutting through the tie bars which extend substantially fully around the support on each of the unit lead frames in the second plurality of unit lead frames.
In one form, the tie bar network consists of a plurality of tie bars that connect the plurality of tie bars, which extend substantially fully around the support on each of the unit lead frames in the second plurality of unit lead frames, to the guide rail.
In one form, the plurality of tie bars which extend substantially fully around the support on each of the unit frames in the second plurality of unit frames have a substantially uniform width.
The method may further include the step of bonding a semiconductor chip to each of the supports on each of the first plurality of unit lead frames.
The semiconductor chips may be bonded to the supports using at least one of a paste and tape.
The step of forming a conductive layer may involve forming a conductive layer through a sputtering process or through an etching process.
The step of resin sealing may be carried out using an epoxy.
The step of separating individual semiconductor devices may involve cutting using a saw.